Integrated circuit (IC) packages provide power and signal interconnects while also providing protection and heat dissipation to IC electronics. For most applications, conventional ICs use lead-frame package designs like a small-outline integrated circuit for power and signal distribution to the printed circuit board (PCB) or substrate. These packages have made surface-mount devices popular. They have, however, difficulty being integrated into performance applications where a high density of interconnects is needed and where size and weight are important factors.
Several alternative packages have emerged to address these issues and limitations to the lead-frame package design. Some examples are flip chip packages (FCPs), chip scale packages (CSPs), stacked dies (STDs), stacked packages (STPs), ball grid array (BGA) packages, and system in packages (SiPs). These alternative packages use solder bumps on the bottom side of the chip to connect to PCBs or substrates. Although the use of solder bumps to connect the PCB or substrate has many advantages over lead-frame package in size and interconnect density, concerns over thermo-mechanical reliability and defective solder bump detection exist because solder bumps are hidden from view. For example, residual stresses on solder bumps after a reflow process can produce significant strain on the solder bumps, leading to bump cracking and delamination.
Some have suggested that as much as 40% of IC package defects are due to soldering problems. Because of this, it is important to monitor solder bump quality after assembly to a PCB or substrate. The ability to detect faults in solder bumps is not only important for quality, but when faults are detected early, corrective action can be taken, reducing costly rework and producing a high quality product at a low cost.
In addition, in conventional fabrication processes, faulty solder joint detection methods are typically done by humans. While generally capable of detecting defective solder joints, the process is generally slow. And when considering that PCBs or substrates have multiple chips that need testing for defects, the testing of different chips can lead to additional inefficiencies.
What is needed, therefore, are improved systems and methods enabling detection of defective solder bumps or joints. It is to the provision of such testing devices, systems, and methods that the various embodiments of the present invention are directed.